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74LVC3G34
Triple buffer gate
Rev. 03 -- 31 January 2005 Product data sheet
1. General description
The 74LVC3G34 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device as translator in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using Ioff. The Ioff circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. The 74LVC3G34 provides three buffers.
2. Features
s s s s Wide supply voltage range from 1.65 V to 5.5 V 5 V tolerant input/output for interfacing with 5 V logic High noise immunity Complies with JEDEC standard: x JESD8-7 (1.65 V to 1.95 V) x JESD8-5 (2.3 V to 2.7 V) x JESD8-B/JESD36 (2.7 V to 3.6 V). ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. 24 mA output drive (VCC = 3.0 V) CMOS low power consumption Latch-up performance exceeds 250 mA Direct interface with TTL levels Multiple package options Specified from -40 C to +85 C and -40 C to +125 C.
s
s s s s s s
Philips Semiconductors
74LVC3G34
Triple buffer gate
3. Quick reference data
Table 1: Quick reference data GND = 0 V; Tamb = 25 C. Symbol Parameter Conditions Min Typ Max Unit VCC = 3.3 V
[1] [2]
VCC = 1.8 V; CL = 30 pF; RL = 1 k tPHL, tPLH propagation delay input nA to V = 2.5 V; C = 30 pF; R = 500 CC L L output nY VCC = 2.7 V; CL = 50 pF; RL = 500 VCC = 3.3 V; CL = 50 pF; RL = 500 VCC = 5.0 V; CL = 50 pF; RL = 500 CI CPD input capacitance power dissipation capacitance per gate
3.8 2.4 2.5 2.2 1.9 2.5 14
-
ns ns ns ns ns pF pF
-
[1]
CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. The condition is VI = GND to VCC.
[2]
4. Ordering information
Table 2: Ordering information Package Temperature range Name 74LVC3G34DP 74LVC3G34DC 74LVC3G34GT -40 C to +125 C -40 C to +125 C -40 C to +125 C TSSOP8 Description plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm Version SOT505-2 Type number
VSSOP8 plastic very thin shrink small outline package; 8 leads; SOT765-1 body width 2.3 mm XSON8 plastic extremely thin small outline package; no leads; SOT833-1 8 terminals; body 1 x 1.95 x 0.5 mm
5. Marking
Table 3: Marking codes Marking code V34 Y34 Y34 Type number 74LVC3G34DP 74LVC3G34DC 74LVC3G34GT
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
2 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
6. Functional diagram
1
1 1 1A 1Y 7
7
2
3Y
3A
6
3
1
5
3
2A
2Y
5 6 1 2
001aaa684 001aaa724
Fig 1. Logic symbol
Fig 2. IEC logic symbol
7. Pinning information
7.1 Pinning
3G34
1A 1 8 VCC
1A 3Y 2A GND
1 2 3 4
001aaa609
8
VCC 1Y 3A 2Y
3Y
2
7
1Y
3G34
7 6 5
2A
3
6
3A
GND
4
5
2Y
001aac024
Transparent top view
Fig 3. Pin configuration VSSOP8 and TSSOP8
Fig 4. Pin configuration XSON8
7.2 Pin description
Table 4: Symbol 1A 3Y 2A GND 2Y 3A 1Y VCC
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Pin description Pin 1 2 3 4 5 6 7 8 Description data input data output data input ground (0 V) data output data input data output supply voltage
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
3 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
8. Functional description
Table 5: Input nA L H
[1] H = HIGH voltage level; L = LOW voltage level.
Function table [1] Output nY L H
9. Limiting values
Table 6: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol VCC VI VO IIK IOK IO ICC, IGND Tstg Ptot
[1] [2]
Parameter supply voltage input voltage output voltage input diode current output diode current output source or sink current VCC or GND current storage temperature power dissipation
Conditions
[1]
Min -0.5 -0.5 -0.5 -0.5 -65
Max +6.5 +6.5 +6.5 -50 50 50 100 +150 300
Unit V V V mA mA mA mA C mW
active mode Power-down mode VI < 0 V VO > VCC or VO < 0 V VO = 0 V to VCC
[1] [2] [1] [2]
VCC + 0.5 V
Tamb = -40 C to +125 C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed. When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
10. Recommended operating conditions
Table 7: VCC VI VO Tamb tr, tf Recommended operating conditions Conditions Min 1.65 0 active mode Power-down mode; VCC = 0 V ambient temperature input rise and fall times VCC = 1.65 V to 2.7 V VCC = 2.7 V to 5.5 V 0 0 -40 0 0 Typ Max 5.5 5.5 VCC 5.5 +125 20 10 Unit V V V V C ns/V ns/V supply voltage input voltage output voltage Symbol Parameter
9397 750 14545
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Product data sheet
Rev. 03 -- 31 January 2005
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Philips Semiconductors
74LVC3G34
Triple buffer gate
11. Static characteristics
Table 8: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Tamb = -40 C to +85 VIH C [1] VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VOH HIGH-level output voltage VI = VIH or VIL IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI Ioff ICC ICC CI VIH input leakage current quiescent supply current additional quiescent supply current per pin input capacitance HIGH-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL LOW-level input voltage VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V
9397 750 14545
Conditions
Min
Typ
Max 0.7 0.8 0.3 x VCC 0.1 0.45 0.3 0.4 0.55 0.55 5 10 10 500 0.7 0.8 0.3 x VCC
Unit V V V V V V V V V V V V V V V V V V V A A A A pF V V V V V V V
HIGH-level input voltage
0.65 x VCC 1.7 2.0 0.7 x VCC VCC - 0.1 1.2 1.9 2.2 2.3 3.8 0.1 0.1 0.1 5 2.5
0.35 x VCC V
VCC = 5.5 V; VI = 5.5 V or GND VCC = 5.5 V; VI = VCC or GND; IO = 0 A VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A
power-off leakage current VCC = 0 V; VI or VO = 5.5 V
Tamb = -40 C to +125 C 0.65 x VCC 1.7 2.0 0.7 x VCC -
0.35 x VCC V
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
5 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
Table 8: Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH Conditions IO = -100 A; VCC = 1.65 V to 5.5 V IO = -4 mA; VCC = 1.65 V IO = -8 mA; VCC = 2.3 V IO = -12 mA; VCC = 2.7 V IO = -24 mA; VCC = 3.0 V IO = -32 mA; VCC = 4.5 V VOL LOW-level output voltage VI = VIH or VIL IO = 100 A; VCC = 1.65 V to 5.5 V IO = 4 mA; VCC = 1.65 V IO = 8 mA; VCC = 2.3 V IO = 12 mA; VCC = 2.7 V IO = 24 mA; VCC = 3.0 V IO = 32 mA; VCC = 4.5 V ILI Ioff ICC ICC input leakage current quiescent supply current additional quiescent supply current per pin VCC = 5.5 V; VI = 5.5 V or GND VCC = 5.5 V; VI = VCC or GND; IO = 0 A VCC = 2.3 V to 5.5 V; VI = VCC - 0.6 V; IO = 0 A power-off leakage current VCC = 0 V; VI or VO = 5.5 V 0.1 0.70 0.45 0.60 0.80 0.80 20 20 40 5000 V V V V V V A A A A Min VCC - 0.1 0.95 1.7 1.9 2.0 3.4 Typ Max Unit V V V V V V HIGH-level output voltage VI = VIH or VIL
[1]
All typical values are measured at Tamb = 25 C.
12. Dynamic characteristics
Table 9: Dynamic characteristics GND = 0 V; test circuit see Figure 6. Symbol tPHL, tPLH Parameter C [1] see Figure 5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V CPD power dissipation capacitance per gate VCC = 3.3 V
[2] [3]
Conditions
Min
Typ
Max
Unit
Tamb = -40 C to +85
propagation delay input nA to output nY
1.0 0.5 0.5 0.5 0.5 -
3.8 2.4 2.5 2.2 1.9 14
8.6 4.4 5.0 4.1 3.2 -
ns ns ns ns ns pF
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
6 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
Table 9: Dynamic characteristics ...continued GND = 0 V; test circuit see Figure 6. Symbol tPHL, tPLH Parameter propagation delay input nA to output nY Conditions see Figure 5 VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V VCC = 2.7 V VCC = 3.0 V to 3.6 V VCC = 4.5 V to 5.5 V
[1] [2] All typical values are measured at nominal VCC and Tamb = 25 C. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL x VCC2 x fo) = sum of outputs. The condition is VI = GND to VCC.
Min
Typ
Max
Unit
Tamb = -40 C to +125 C 1.0 0.5 0.5 0.5 0.5 10.8 5.5 6.3 5.1 4.0 ns ns ns ns ns
[3]
13. AC waveforms
VI nA input GND tPLH VOH nY output VOL
001aaa725
VM
VM
tPHL
VM
VM
Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage drop that occur with the output load.
Fig 5. Input nA to output nY propagation delay times Table 10: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Measurement points Input VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC Output VM 0.5 x VCC 0.5 x VCC 1.5 V 1.5 V 0.5 x VCC
Supply voltage
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
7 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
mna616
Test data is given in Table 11. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistor.
Fig 6. Load circuitry for switching times Table 11: VCC 1.65 V to 1.95 V 2.3 V to 2.7 V 2.7 V 3.0 V to 3.6 V 4.5 V to 5.5 V Test data Input VI VCC VCC 2.7 V 2.7 V VCC tr, tf 2.0 ns 2.0 ns 2.5 ns 2.5 ns 2.5 ns Load CL 30 pF 30 pF 50 pF 50 pF 50 pF RL 1 k 500 500 500 500 VEXT tPLH, tPHL open open open open open
Supply voltage
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
8 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
14. Package outline
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
Fig 7. Package outline SOT505-2 (TSSOP8)
9397 750 14545 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
9 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
D
E
A X
c y HE vMA
Z
8
5
Q A pin 1 index A2 A1 (A3) Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1 A1 0.15 0.00 A2 0.85 0.60 A3 0.12 bp 0.27 0.17 c 0.23 0.08 D(1) 2.1 1.9 E(2) 2.4 2.2 e 0.5 HE 3.2 3.0 L 0.4 Lp 0.40 0.15 Q 0.21 0.19 v 0.2 w 0.13 y 0.1 Z(1) 0.4 0.1 8 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT765-1 REFERENCES IEC JEDEC MO-187 JEITA EUROPEAN PROJECTION
ISSUE DATE 02-06-07
Fig 8. Package outline SOT765-1 (VSSOP8)
9397 750 14545 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
10 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
SOT833-1
1
2
3
b 4 4x L
(2)
L1
e
8 e1
7 e1
6 e1
5
8x
(2)
A
A1 D
E
terminal 1 index area 0 DIMENSIONS (mm are the original dimensions) UNIT mm A (1) max 0.5 A1 max 0.04 b 0.25 0.17 D 2.0 1.9 E 1.05 0.95 e 0.6 e1 0.5 L 0.35 0.27 L1 0.40 0.32 1 scale 2 mm
Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. OUTLINE VERSION SOT833-1 REFERENCES IEC --JEDEC MO-252 JEITA --EUROPEAN PROJECTION ISSUE DATE 04-07-22 04-11-09
Fig 9. Package outline SOT833-1 (XSON8)
9397 750 14545 (c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
11 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
15. Revision history
Table 12: Revision history Release date 20050131 Data sheet status Product data sheet Product data sheet Product data sheet Change notice Doc. number 9397 750 14545 9397 750 13794 9397 750 13076 Supersedes 74LVC3G34_2 74LVC3G34_1 Document ID 74LVC3G34_3 Modifications: 74LVC3G34_2 74LVC3G34_1
*
Changed: type number 74LVC3G34GT.
20041027 20040429
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
12 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
16. Data sheet status
Level I II Data sheet status [1] Objective data Preliminary data Product status [2] [3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
III
Product data
Production
[1] [2] [3]
Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
17. Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
18. Disclaimers
Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
19. Contact information
For additional information, please visit: http://www.semiconductors.philips.com For sales office addresses, send an email to: sales.addresses@www.semiconductors.philips.com
9397 750 14545
(c) Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 03 -- 31 January 2005
13 of 14
Philips Semiconductors
74LVC3G34
Triple buffer gate
20. Contents
1 2 3 4 5 6 7 7.1 7.2 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information . . . . . . . . . . . . . . . . . . . . 13
(c) Koninklijke Philips Electronics N.V. 2005
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 31 January 2005 Document number: 9397 750 14545
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